So, i've submitted my abstract. Now what?

This was my first time ever, that i submitted an abstract for a conference. Less than an hour before i really submitted it through the conference's website, i sent it to my supervisors. Quite surprisingly, one of my supervisor gave a very positive response. This never happens from him. I mean, the good response. Anyway, it does make this cold cloudy day just a bit brighter, for me at least... :-)

This is the abstract:

Comparison Framework for Low Swing On-Chip Interconnect Circuits

There has been many low-swing on-chip interconnect signaling techniques introduced to tackle the problem of inverse-scaling effect of on-chip wires. This paper proposes a comparison framework using SPICE-based simulations on the 90nm technology node, which is needed to assess the effectiveness of a certain interconnect technique over the others with a high degree of objectiveness and accuracy. Three low-swing techniques are included in the comparison, i.e. conventional level converter (CLC), pseudodifferential signaling, and current-mode signaling (CM). These techniques were chosen to represent significantly different driver and receiver topologies, where CLC uses inverter drivers, pseudodifferential are based on source-follower drivers, and CM has a low impedance termination at receiver end. In addition, an optimized full-swing repeater-based technique is included as a baseline for comparison. Wires are modeled as cascaded RLC segments, and the simulation setup will incorporate cross-capacitance and cross-inductance effect from neighbouring wires. Preliminary simulations on global wires show that inductance affects delay only up to 9%, however its effects on noise cannot be neglected. The main contribution of this paper is the identification of circuit and wire design parameters that affects performances the most, leading to a design guideline with reduced set of design variables for delay or energy optimization of each technique. Furthermore, trade-off between energy and delay using the optimization processes will be explored, resulting in a more objective comparison of different interconnect techniques in the energy-delay space.

So... all i need to do now is simple. Show results (yeah, easy for me to say!), and write the bloody paper (due on early november, i think -- if they accept my abstract that is...). Problem is, it's going to be one hell of a research thing... imagine the torture, imagine the sleepless sunday nights with Kim and Kushal, and the horrifying maths involved in the so-called circuit optimization techniques for power with delay constraints, including all those crosstalk noise and inductance effects. Not to mention the painfully slow parametric sweeps run by the sluggerish cadence analog artist tool, and those stupid traps of teeny weeny typos i might be silly enough to actualy fall into again and again, wasting all those precious hours and computing horse power for nothing. And the mystery of inductance, dude... it IS still a big mystery.

Anyway, one step at a time should do the trick. I've pretty much done the repeater insertion technique, and CLC. Probably, it's useful to know more about current mode signaling optimization? You reckon?

Hmm.... i better start reading more and more papers and books.... (have i told you i spent $15 for photocopying some chapters from IMPORTANT books i found at UTS library last night? yep. Their book collections are awesome. i couldn't stop wondering why our library aren't as good. anyway, must read them now, otherwise they'll end up in the bottom of a pile full of papers locked inside my drawer)

Research update 26/6/07

It's been a while now since i last talked about my thesis progress. Not that i was too busy working on it that i had no time to blog, it's just that there hasn't been any good results yet.

Yesterday i had my third progress review, and it turned okay. Not too bad. They gave me satisfactory mark for the research progress. But still, heaps of works needs to be done, and quickly. I set my own deadline for submission on late November. At first they thought it's too quick, but they agreed anyway.

As you might already know, i'm working on low power on-chip interconnects. In english it might translate as "efficient wires inside microchips". There's nothing special about it. It's only about how to send signals through wires inside those stupid tiny chips with the lowest power consumption possible, while maintaining the required need for speed ;-)

The original idea was that i should come up with a new circuit design that at least can solve this problem, a new circuit that can outperform others. But bloody oath, that's too hard mate, even for an experienced designer. And not to mention the limited time i have now, it seems more impossible to accomplish this.

So,

My supervisor and i agreed, in order to finish this silly thesis on time, i would now focus on doing comparisons of different interconnect circuit topologies, in an highly accurate way. We've switched to this focus about two months ago, and work is still on progress. Well, actually the initial works i did at the very beginning of my masters was no different than what i'm doing now. But at that time, it wasn't considered too crucial. It was meant only to be a... some sort of a leaping point, for a new circuit design. So, not much attention was put into that, resulting in very crude work, with low level of accuracy.

Apparently, that's a big mistake. Even if my research goal now was still unchanged, i.e. making new circuit designs, this step must have been taken seriously with no rush, as it gives very valuable insights on how to do things properly, including how to design new designs effectively.

What i'm doing now is this. There are many interconnect signaling schemes out there, i absolutely don't know whether they are actually implemented on real designs or not, i don't really care anyway. But that's no problem. My work will compare at least 3 low power designs: 1 ordinary reduced swing drivers, 1 pseudodifferential circuit, and 1 current mode signaling. Plus 1 more from the normal full swing repeated interconnect.

Now what makes it interesting is, i need to optimize each of them, and i really do want to know how this optimization can be done. I mean, what factors affects most to energy and delay? What are the most important design parameters to look at? In a circuit, there are so many design parameters that you can change in order to get a best design. But that's too much. There must be a reduced set of design parameters to aid the design of optimized circuits, either delay optimized or energy optimized.

My work had at least formulated a methodology based on literature review, on how to optimize the normal full swing repeated interconnect, with the possibility of it to be implemented on the conventional low level converter technique.

The remaining tasks are even harder: finding a way to optimize pseudodifferential circuits and current mode signaling.

Just these two. Wish me luck.

Abad 21 begini, masih ngurusi begituan??

Ingat pelajaran elektronika SMA tidak? Ingat kan ya soal resistor, kapasitor, kuat arus, daya, dll?

Itu pelajaran dasar elektronika. Dasar sekali. Sudah jaman dulu banget orang nemu itu.

Tapi silakan kaget. Di depan saya skrg ada paper berjudul "Resistive Power in CMOS Circuits" yang dipublish tahun 2004. Heh? Setelat itukah paper ini harus keluar? Atau mungkin hal sepele semacam ini masih bisa dijadikan perdebatan sampai sekarang?

Ternyata bisa.

Salah satu kalimat di paper itu berbunyi begini:

"Confusion, however, exists as to whether and how to consider resistive I square R power losses within the interconnect line."

Haha... tahu aja ni orang. I am one of those confused, to tell you the truth...

Lalu, ada tulisan begini:

"Greater line resistance can also increase the short-circuit power dissipation of the driver and the load gate."

Baruuu tadi siang diskusi dengan dosen. Beliau berpendapat bahwa line resistance tidak akan ngefek ke driver.

Oke, yang kedua ini mungkin bukan pelajaran SMA, tapi seharusnya hal-hal sepele seperti ini sudah ada kepastian nya dulu sekali, ketika teknologi CMOS mulai diperkenalkan awal 60-an dan booming awal 90-an... atau ... kapan ya CMOS mulai booming? Hmm... mungkin memang teknologi CMOS masih agak muda ya pancen e... bukti nya di pelajaran SMA tidak disinggung dulu itu? Sekarang sudah masuk belum ya?

Anyway, beberapa journal paper yang membahas teori dasar sederhana semacam ini banyak yang masih dipublish akhir2 ini... di abad 21 bayangkan... di jaman orang sudah sangat melesat jauh nemu cloning, nanotubes, micromachines, quantum computing, dll...

Moral of the story: publish yuk? :D

So you want to take a research degree...

That's good. There's absolutely nothing wrong with doing a PhD or a master's degree with research. But if you decide to do so, just make sure:
1. You believe that the 2-5 years time you spend is really worth it.
2. You have a strong interest in the research topic you're about to take.
3. Some supporting background, may that be experience or knowledge, in you research topic would definitely help.
4. Better get a really good supervisor for your thesis work. By saying good, i mean that he/she should at least have followed the latest development on the subject. Or even better, she/he had actually worked with significant experience in the topic you are about to dive in.
5. Being idealistic is a good thing. But sooner or later you will inevitably learn that being realistic helps more often ;-)

So good luck to all. And to myself... :-(

Briliant idea, but still not there just yet...

This is an idea of a current-sensing-powered-from-the-driver-circuit from my supervisor, which i tried to implement:



And this is what the test results looks like:


(the wire is a 1um wide 3mm long metal, with a full swing CMOS driver)

Looks ugly? Yup. You can say that again. Especially the triangle wave... that's horrible.

Very well. I'll keep trying.

Modeling the wires: a simple one

Speed or power. That was the question we asked on our last post. What if we want BOTH?

That's human nature. Human beings tend to be greedy. Sometimes a bit cruel too (e.g. i just squished a mozzy who wanted death: it bit me on my arm :D)

Back to interconnects, a fast and low power one that is. How do we get both of them?

In engineering, this daunting task is often called optimization. To do some silly optimization, one should model the problem with some mathematical expressions. To make life easy (that's what we engineers are here for anyway), modeling of physical properties and electrical characteristics of devices are normally made as simple as possible: simplification and approximation must be used whenever possible.

Alright, let us start with some maths from now.

Bakoglu, 22 years ago at 1985 modeled the wire system as consisting of a resistive driver, a lumped RC network as the wire, and a capacitive load at the receiver. You can read his paper titled "Optimal Interconnection Circuits for VLSI" for more details. From the way he drew the symbol of the load, which was the gate of a MOS transistor, it was obvious that voltage mode signaling was assumed.

A good approximation of the wire delay, he said, is:

T = 1.0 * Rint * Cint + 2.3 * (Rtr * Cint + Rtr * Cl + Rint * Cl)

and neglecting Cl, then

T = (2.3 Rtr + Rint) Cint

where Rtr = driver resistance, Rint = wire resistance, Cint = wire capacitance to ground, and Cl = load capacitance.

The driver's resistance, which is also the on-resistance of a MOS transistor is:

Rtr = (L / W) / (u * Cgox * Vdd)

And the resistance of the wire is a bit simpler, perhaps we all know this one from high school:

Rint = resistivity * Lmax / (Wint * H)

Wint times H is simply the cross-sectional area of the wire.

Now, he formulated the optimal cross-sectional area of the wire to be:

Wint * H = resistivity * Lmax / (2.3 * Rtr)

It seems that he chose the delay from wires to be roughly equal to the delay caused by the driver. Normally, the H is fixed for a certain technology. So the variable parameter we can play on is the width of the wire, Wint. The above formula enables us to find a minimum value of the interconnect width, with a reasonably low delay as possible. This idea is cited in Adler's paper "Repeater Design to Reduce Delay and Power in Resistive Interconnect" (1998).

Furthermore in his paper, Bakoglu explains about repeaters and inverter chains (cascaded drivers). Combining both will produce the shortest delay possible, where the extreme lower limit is the propagation delay of a lossless transmission line, where the speed is:

v = c / SQRT(dielectric constant of medium)

Interconnects... speed or power?

For general integrated circuit logics, why are low voltage being used?
- First reason: to save power.
- It follows CMOS technology scaling. That is, shrinking sizes of transistor dimensions. Which means, more transistors can be fit into a chip. Which also means, chips can get smarter, and faster at the same time.

But, what about low voltage interconnects? What about on-chip wires??
- Yes, their size won't get smaller. In fact, they will get more complex and probably longer since you will now have much more things to connect to inside a chip, and not to mention the fact that they make chips a bit bigger nowadays?
- So, yes. It's not a good news for interconnects. Yes, low voltage will save power too in the case of interconnects, BUT due to the above circumstances, longer delays will occur... and higher noise interference?

So at least, we had identified two contradictive problems for interconnects: speed and power.

Naturally, if you just follow the technology scaling trend without doing any clever solutions to the interconnect, then these interconnects will get slower and more power consumptive.

Now, it all depends on what is it that you actually want? Do you want speed? Or are you more concerned with power?

Pengumuman: Blog baru ku

Dari pengalamanku... kalau kita punya lebih dari satu blog, biasanya hanya salah satu yang rajin kita isi dan kelola. Yang satunya? Males. Just to let you know, diriku punya blog di FS, ada lagi blog dari Yahoo (namanya 360 bukan ya?), terus ada lagi yang lumayan baru dari VOX. Tapi ya itu... males diisi.

Dan skrg keadaan ini semakin kuperparah dengan membuat satu blog lagi.. khusus tentang perkembangan thesis ku. Kunamakan blog itu Irfan's Thesis Progress. Terdengar membosankan? Memang iya. Semoga saja niat ku bisa kujalankan dengan konsisten sampai thesis ku selesai. Amin.