Wednesday, June 27, 2007

So, i've submitted my abstract. Now what?

This was my first time ever, that i submitted an abstract for a conference. Less than an hour before i really submitted it through the conference's website, i sent it to my supervisors. Quite surprisingly, one of my supervisor gave a very positive response. This never happens from him. I mean, the good response. Anyway, it does make this cold cloudy day just a bit brighter, for me at least... :-)

This is the abstract:
Comparison Framework for Low Swing On-Chip Interconnect Circuits

There has been many low-swing on-chip interconnect signaling techniques introduced to tackle the problem of inverse-scaling effect of on-chip wires. This paper proposes a comparison framework using SPICE-based simulations on the 90nm technology node, which is needed to assess the effectiveness of a certain interconnect technique over the others with a high degree of objectiveness and accuracy. Three low-swing techniques are included in the comparison, i.e. conventional level converter (CLC), pseudodifferential signaling, and current-mode signaling (CM). These techniques were chosen to represent significantly different driver and receiver topologies, where CLC uses inverter drivers, pseudodifferential are based on source-follower drivers, and CM has a low impedance termination at receiver end. In addition, an optimized full-swing repeater-based technique is included as a baseline for comparison. Wires are modeled as cascaded RLC segments, and the simulation setup will incorporate cross-capacitance and cross-inductance effect from neighbouring wires. Preliminary simulations on global wires show that inductance affects delay only up to 9%, however its effects on noise cannot be neglected. The main contribution of this paper is the identification of circuit and wire design parameters that affects performances the most, leading to a design guideline with reduced set of design variables for delay or energy optimization of each technique. Furthermore, trade-off between energy and delay using the optimization processes will be explored, resulting in a more objective comparison of different interconnect techniques in the energy-delay space.
So... all i need to do now is simple. Show results (yeah, easy for me to say!), and write the bloody paper (due on early november, i think -- if they accept my abstract that is...). Problem is, it's going to be one hell of a research thing... imagine the torture, imagine the sleepless sunday nights with Kim and Kushal, and the horrifying maths involved in the so-called circuit optimization techniques for power with delay constraints, including all those crosstalk noise and inductance effects. Not to mention the painfully slow parametric sweeps run by the sluggerish cadence analog artist tool, and those stupid traps of teeny weeny typos i might be silly enough to actualy fall into again and again, wasting all those precious hours and computing horse power for nothing. And the mystery of inductance, dude... it IS still a big mystery.

Anyway, one step at a time should do the trick. I've pretty much done the repeater insertion technique, and CLC. Probably, it's useful to know more about current mode signaling optimization? You reckon?

Hmm.... i better start reading more and more papers and books.... (have i told you i spent $15 for photocopying some chapters from IMPORTANT books i found at UTS library last night? yep. Their book collections are awesome. i couldn't stop wondering why our library aren't as good. anyway, must read them now, otherwise they'll end up in the bottom of a pile full of papers locked inside my drawer)


Tuesday, June 26, 2007

Research update 26/6/07

It's been a while now since i last talked about my thesis progress. Not that i was too busy working on it that i had no time to blog, it's just that there hasn't been any good results yet.

Yesterday i had my third progress review, and it turned okay. Not too bad. They gave me satisfactory mark for the research progress. But still, heaps of works needs to be done, and quickly. I set my own deadline for submission on late November. At first they thought it's too quick, but they agreed anyway.

As you might already know, i'm working on low power on-chip interconnects. In english it might translate as "efficient wires inside microchips". There's nothing special about it. It's only about how to send signals through wires inside those stupid tiny chips with the lowest power consumption possible, while maintaining the required need for speed ;-)

The original idea was that i should come up with a new circuit design that at least can solve this problem, a new circuit that can outperform others. But bloody oath, that's too hard mate, even for an experienced designer. And not to mention the limited time i have now, it seems more impossible to accomplish this.


My supervisor and i agreed, in order to finish this silly thesis on time, i would now focus on doing comparisons of different interconnect circuit topologies, in an highly accurate way. We've switched to this focus about two months ago, and work is still on progress. Well, actually the initial works i did at the very beginning of my masters was no different than what i'm doing now. But at that time, it wasn't considered too crucial. It was meant only to be a... some sort of a leaping point, for a new circuit design. So, not much attention was put into that, resulting in very crude work, with low level of accuracy.

Apparently, that's a big mistake. Even if my research goal now was still unchanged, i.e. making new circuit designs, this step must have been taken seriously with no rush, as it gives very valuable insights on how to do things properly, including how to design new designs effectively.

What i'm doing now is this. There are many interconnect signaling schemes out there, i absolutely don't know whether they are actually implemented on real designs or not, i don't really care anyway. But that's no problem. My work will compare at least 3 low power designs: 1 ordinary reduced swing drivers, 1 pseudodifferential circuit, and 1 current mode signaling. Plus 1 more from the normal full swing repeated interconnect.

Now what makes it interesting is, i need to optimize each of them, and i really do want to know how this optimization can be done. I mean, what factors affects most to energy and delay? What are the most important design parameters to look at? In a circuit, there are so many design parameters that you can change in order to get a best design. But that's too much. There must be a reduced set of design parameters to aid the design of optimized circuits, either delay optimized or energy optimized.

My work had at least formulated a methodology based on literature review, on how to optimize the normal full swing repeated interconnect, with the possibility of it to be implemented on the conventional low level converter technique.

The remaining tasks are even harder: finding a way to optimize pseudodifferential circuits and current mode signaling.

Just these two. Wish me luck.


Sunday, June 24, 2007

Terima kasih.

There's nothing else i can do but to say "Terima kasih."

Terlalu banyak orang di dunia ini yang... entah kenapa... sangat baik ke diriku. Pertama, ibuku bapakku dan masku. Lalu keluarga ku yang lain. Walaupun ini adalah wajar, tapi tetap, tetap saja jasa mereka tidak bisa dianggap sepele.

Yang tidak wajar, adalah kalau ada orang yang tidak terlalu kamu kenal, tapi mereka jadi baik ke kita. Kebanyakan teman2 ku baik begitu, sejak SD, walaupun tidak semua. Oh iya, jadi ingat. Jaman SD dulu, waktu aku di SD Kintelan dalam keadaan tdk punya teman byk dan tdk bisa berbahasa Indonesia, ada teman yang hampir tiap hari memberikan aku kelereng. Entah apa motivasi nya, yg jelas koleksi kelerengku waktu itu jadi banyak gara2 dia.

Dunia ini penuh dengan orang baik. Tidak pandang tempat. Desa, kota, Indonesia, luar negeri... semua dipenuhi orang-orang baik.

Di Sydney, sewaktu kecil, rumahku pernah kemasukan maling, dan saat itu hanya aku yang ada di rumah. Maling ini baik, dia mengambil betamax player dari kamar dengan ramah, bilang ke aku kalau dia temannya bapak. Lalu dia pergi tanpa melukaiku sedikitpun.

Di jogja, selain teman dermawan kelereng tadi, pernah suatu ketika aku melanggar lampu merah di ringroad barat. Tiba2, ada polisi meminta aku berhenti. Beliau mengingatkan ttg kesalahanku, lalu dia bersedia membantu menguruskan pengadilannya setelah kubayar sekian puluh ribu rupiah. Bandingkan dengan denda termahal yg pernah kubayar di Sydney sini cuma karena parkir mobil di pojokan persimpangan jalan: AU$177. Bebas korupsi sih memang yang ini, tapi kan rugi, lha mahal sekali.

Di Jakarta, bertolak belakang dengan pandangan umum bahwa kota ini tidak ramah, justru yg kutemui kebanyakan orang ramah. Tanya arah dan tanya jalur bus, jawabannya selalu jujur. Jauh dari kesan manusia egois. Manusia Jakarta sangat ramah. Ini yang kutemui sih. Tapi dari 12 juta orang penduduk kota ini, entah lah, menurut statistik, harusnya banyak juga yang jahat....

Tapi, di antara semua teman/kenalan itu, ada satu teman yang saat ini paling ingin kuberi ucapan terima kasih. Beliau adalah supervisorku (inisialnya saja yg kukasih: TL). Tiap kali berdiskusi dgn beliau, tidak terasa 1 jam selalu berlalu, dgn proporsi beliau yang lebih banyak memberikan ide, saran, dan pelajaran. Entahlah apa yang bakal terjadi tanpa beliau, bisa saja tesis ku lebih terancam lagi dibandingkan kondisi nya yg skrg yg sebenarnya memang sdh terancam :D

Jadi ingat lagu nya Julie Andrews "Something good"

Perhaps I had a wicked childhood

Perhaps I had a miserable youth

But somewhere in my wicked, miserable past

There must have been a moment of truth

For here you are

Standing there

Loving me

Whether or not you should

So somewhere in my youth or childhood

I must have done something good

Entahlah. Alhamdulillahirobbil'alamin.