So, i've submitted my abstract. Now what?

This was my first time ever, that i submitted an abstract for a conference. Less than an hour before i really submitted it through the conference's website, i sent it to my supervisors. Quite surprisingly, one of my supervisor gave a very positive response. This never happens from him. I mean, the good response. Anyway, it does make this cold cloudy day just a bit brighter, for me at least... :-)

This is the abstract:

Comparison Framework for Low Swing On-Chip Interconnect Circuits

There has been many low-swing on-chip interconnect signaling techniques introduced to tackle the problem of inverse-scaling effect of on-chip wires. This paper proposes a comparison framework using SPICE-based simulations on the 90nm technology node, which is needed to assess the effectiveness of a certain interconnect technique over the others with a high degree of objectiveness and accuracy. Three low-swing techniques are included in the comparison, i.e. conventional level converter (CLC), pseudodifferential signaling, and current-mode signaling (CM). These techniques were chosen to represent significantly different driver and receiver topologies, where CLC uses inverter drivers, pseudodifferential are based on source-follower drivers, and CM has a low impedance termination at receiver end. In addition, an optimized full-swing repeater-based technique is included as a baseline for comparison. Wires are modeled as cascaded RLC segments, and the simulation setup will incorporate cross-capacitance and cross-inductance effect from neighbouring wires. Preliminary simulations on global wires show that inductance affects delay only up to 9%, however its effects on noise cannot be neglected. The main contribution of this paper is the identification of circuit and wire design parameters that affects performances the most, leading to a design guideline with reduced set of design variables for delay or energy optimization of each technique. Furthermore, trade-off between energy and delay using the optimization processes will be explored, resulting in a more objective comparison of different interconnect techniques in the energy-delay space.

So... all i need to do now is simple. Show results (yeah, easy for me to say!), and write the bloody paper (due on early november, i think -- if they accept my abstract that is...). Problem is, it's going to be one hell of a research thing... imagine the torture, imagine the sleepless sunday nights with Kim and Kushal, and the horrifying maths involved in the so-called circuit optimization techniques for power with delay constraints, including all those crosstalk noise and inductance effects. Not to mention the painfully slow parametric sweeps run by the sluggerish cadence analog artist tool, and those stupid traps of teeny weeny typos i might be silly enough to actualy fall into again and again, wasting all those precious hours and computing horse power for nothing. And the mystery of inductance, dude... it IS still a big mystery.

Anyway, one step at a time should do the trick. I've pretty much done the repeater insertion technique, and CLC. Probably, it's useful to know more about current mode signaling optimization? You reckon?

Hmm.... i better start reading more and more papers and books.... (have i told you i spent $15 for photocopying some chapters from IMPORTANT books i found at UTS library last night? yep. Their book collections are awesome. i couldn't stop wondering why our library aren't as good. anyway, must read them now, otherwise they'll end up in the bottom of a pile full of papers locked inside my drawer)