Research update 26/6/07
It's been a while now since i last talked about my thesis progress. Not that i was too busy working on it that i had no time to blog, it's just that there hasn't been any good results yet.
Yesterday i had my third progress review, and it turned okay. Not too bad. They gave me satisfactory mark for the research progress. But still, heaps of works needs to be done, and quickly. I set my own deadline for submission on late November. At first they thought it's too quick, but they agreed anyway.
As you might already know, i'm working on low power on-chip interconnects. In english it might translate as "efficient wires inside microchips". There's nothing special about it. It's only about how to send signals through wires inside those stupid tiny chips with the lowest power consumption possible, while maintaining the required need for speed ;-)
The original idea was that i should come up with a new circuit design that at least can solve this problem, a new circuit that can outperform others. But bloody oath, that's too hard mate, even for an experienced designer. And not to mention the limited time i have now, it seems more impossible to accomplish this.
So,
My supervisor and i agreed, in order to finish this silly thesis on time, i would now focus on doing comparisons of different interconnect circuit topologies, in an highly accurate way. We've switched to this focus about two months ago, and work is still on progress. Well, actually the initial works i did at the very beginning of my masters was no different than what i'm doing now. But at that time, it wasn't considered too crucial. It was meant only to be a... some sort of a leaping point, for a new circuit design. So, not much attention was put into that, resulting in very crude work, with low level of accuracy.
Apparently, that's a big mistake. Even if my research goal now was still unchanged, i.e. making new circuit designs, this step must have been taken seriously with no rush, as it gives very valuable insights on how to do things properly, including how to design new designs effectively.
What i'm doing now is this. There are many interconnect signaling schemes out there, i absolutely don't know whether they are actually implemented on real designs or not, i don't really care anyway. But that's no problem. My work will compare at least 3 low power designs: 1 ordinary reduced swing drivers, 1 pseudodifferential circuit, and 1 current mode signaling. Plus 1 more from the normal full swing repeated interconnect.
Now what makes it interesting is, i need to optimize each of them, and i really do want to know how this optimization can be done. I mean, what factors affects most to energy and delay? What are the most important design parameters to look at? In a circuit, there are so many design parameters that you can change in order to get a best design. But that's too much. There must be a reduced set of design parameters to aid the design of optimized circuits, either delay optimized or energy optimized.
My work had at least formulated a methodology based on literature review, on how to optimize the normal full swing repeated interconnect, with the possibility of it to be implemented on the conventional low level converter technique.
The remaining tasks are even harder: finding a way to optimize pseudodifferential circuits and current mode signaling.
Just these two. Wish me luck.
Yesterday i had my third progress review, and it turned okay. Not too bad. They gave me satisfactory mark for the research progress. But still, heaps of works needs to be done, and quickly. I set my own deadline for submission on late November. At first they thought it's too quick, but they agreed anyway.
As you might already know, i'm working on low power on-chip interconnects. In english it might translate as "efficient wires inside microchips". There's nothing special about it. It's only about how to send signals through wires inside those stupid tiny chips with the lowest power consumption possible, while maintaining the required need for speed ;-)
The original idea was that i should come up with a new circuit design that at least can solve this problem, a new circuit that can outperform others. But bloody oath, that's too hard mate, even for an experienced designer. And not to mention the limited time i have now, it seems more impossible to accomplish this.
So,
My supervisor and i agreed, in order to finish this silly thesis on time, i would now focus on doing comparisons of different interconnect circuit topologies, in an highly accurate way. We've switched to this focus about two months ago, and work is still on progress. Well, actually the initial works i did at the very beginning of my masters was no different than what i'm doing now. But at that time, it wasn't considered too crucial. It was meant only to be a... some sort of a leaping point, for a new circuit design. So, not much attention was put into that, resulting in very crude work, with low level of accuracy.
Apparently, that's a big mistake. Even if my research goal now was still unchanged, i.e. making new circuit designs, this step must have been taken seriously with no rush, as it gives very valuable insights on how to do things properly, including how to design new designs effectively.
What i'm doing now is this. There are many interconnect signaling schemes out there, i absolutely don't know whether they are actually implemented on real designs or not, i don't really care anyway. But that's no problem. My work will compare at least 3 low power designs: 1 ordinary reduced swing drivers, 1 pseudodifferential circuit, and 1 current mode signaling. Plus 1 more from the normal full swing repeated interconnect.
Now what makes it interesting is, i need to optimize each of them, and i really do want to know how this optimization can be done. I mean, what factors affects most to energy and delay? What are the most important design parameters to look at? In a circuit, there are so many design parameters that you can change in order to get a best design. But that's too much. There must be a reduced set of design parameters to aid the design of optimized circuits, either delay optimized or energy optimized.
My work had at least formulated a methodology based on literature review, on how to optimize the normal full swing repeated interconnect, with the possibility of it to be implemented on the conventional low level converter technique.
The remaining tasks are even harder: finding a way to optimize pseudodifferential circuits and current mode signaling.
Just these two. Wish me luck.
Labels: thesis
posted by Irfan at 11:04 am
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