Saturday, August 24, 2013

A bit about my PhD

I know this is far too late to start blogging about my PhD, which I already have started since Jan 2012 ago. But I might regret not to write about it anyway one day later who knows, so it may not harm to start writing about it now.

My PhD is funded by the Indonesian government directorate general of higher education. I have tried to apply for other scholarships during my time at Universitas Gadjah Mada, and failed, but maybe that is what is meant to be: that I would have less problems moving to Institut Teknologi Sepuluh Nopember mid 2011. My research area is basically microelectronics, even though as lecturer in UGM most of my research projects were embedded systems. As I looked for PhD topics and potential supervisors, I got interested at one point to a PhD opening by a professor at Sydney University. Long story short, I end up having that exact same PhD topic (they are practically the same project) but by his collaborator and also former student, at UNSW. So, here I am now, doing PhD in microelectronics, at The University of New South Wales.

Electrical Engineering Building, UNSW, Kensington. The window of my office room is one of the ones seen here.


I joined the nanolab group not long before they start on a 180 CMOS process chip tape out plan. As I was new, I get to join with other friends on working on a design that has been started previously in the group: a sigma delta modulation digital to analog converter.
An early implementation of this design was targeted at a 65nm process, and it was found to be difficult to build an 8-level internal DAC with the required linearity of a 16-bit converter. My co-supervisor and industrial partner came up with an idea to solve this, instead of using a current steering DAC with cascoding, we use something significantly different, involving no current sources, and also much simpler. Whether this solution is actually better, that may be a different story. But all I can report now is that it definitely "works" (lab-tested and silicon-proven).

The early part of my first semester of my PhD was basically setting up all the proper tools to work with, and most of which was done by our industrial partner. We use Cadence for circuit design and simulation, but I can remember using gEDA and ngspice a few times in my first few weeks before I got access to Cadence, to do some quick simulations on the DAC, trying to familiarize myself with the problems we need to face. We use Matlab to do quick simulations, even though Python seems to be preferred by some in the group.

The rest of the semester was mainly porting the DAC which had already been designed in 65nm into 180nm, all the way from schematics to full layout. The "only" part that I needed to design myself was the final stage internal DAC, and this is the analog part of the system. Speaking of analog, this is exactly the topic of my PhD: analog circuits in nanometer CMOS technology. This is of course still very general, and it took a while to come up with something to focus on among the many alternatives we initially thought of. My initial plan, and proposal, was to explore alternative techniques to implement analog circuit, preferably with more digital-like structures. However I have always insisted on having a case study, or specific application of these analog techniques that (hopefully) I propose. Otherwise, I may repeat something I had during my Masters program: building a "general" circuit that needs to be "the best", more like an optimization task but with unclear theoretical limitations to what can actually be achieved. And this is, from my experience, can get boring. I hope by having a particular application, it could get a little more "exciting"?

When my first annual progress review came in October 2012, we have already completed our first chip tapeout, so the review panel were happy about this and I got satisfactory result (the comments I remember was I am on track for three years completion). Each of us from nanolab also submitted papers to ISCAS 2013 Beijing, but just few got accepted. The paper that I submitted to ISCAS was rejected, and after revision I submitted it to another confernce and got acceptance at TENCON Spring 2013 Sydney. An extension to this first paper, focusing on the design trade off of the current steering DAC version of the internal DAC we implemented, was submitted to MWSCAS 2013 Columbus OH and got accepted. At least I am still co-author of one of the papers accepted at ISCAS 2013, I feel thankful for this.

IEEE Midwest Symposium on Circuits and Systems 2013, Ohio State University. The Buckeye Bullet motorcycle version from Ohio State University is being displayed.

The chip came in late 2012 (perhaps December), and I quickly started setting up the test benches. I must thank our industrial partner for all the test boards and control software script. He also managed to test the chip first in Brazil at that time, demonstrating that it works, so I can simply follow what he did to do the rest.

My wife and kid joined me in that late December 2012. As a father, reuniting with family is not just an ordinary event. It is a mix of joy, and of course it is somewhat a responsibility: as long as it is possible for us to be physically together, we should take that chance. So in terms of PhD work progress, it really is becoming a real challenge to it. I may have stayed years in Australia before, but living WITH my wife and kid, without any other family assisting us here, is really something new to me. It took time for me to adjust to this new condition, and I am probably still in that phase now. My wife is also doing a PhD at UNSW, I imagine it must also be very challenging for her too.

It is now August 2013 and I do not have any major breakthrough since the last chip tape out. Apart from chip test results (which is also still not conclusive yet) and playing around with basic circuit simulations, I have not made any new circuit designs yet. My supervisor did mention her concerns a few months ago, that I have not come up with what I can claim to be the "main contribution" of my PhD. And that is true, it really is difficult to even plan this. Okay, that may be an exaggeration, we did have many ideas before, but many did not seem to continue into anything meaningful. Most probably this was due to my inexperience and lack of detailed knowledge of the recent trends in our field of circuits and systems. The other thing is that these ideas would ideally be a match between what we are able to do and what our industrial partner is also interested in.

Chip testing

Nevertheless, despite no breakthroughs, it seems that I can feel confident enough now when I talk to my supervisors about the specific topic of research I am currently doing. The topic I am particularly focusing now is the continuous-time (CT) delta-sigma modulation ADC, emphasizing on the use of a "different" transconductor (no, I don't have a "different" one yet). Transconductors are basic building blocks of analog circuits. They are used in op amps, filters, and in my case, we want to use them in a delta-sigma ADC. My friend in nanolab is using a particular type of transconductor in a pipeline ADC, so it would make sense to me to work on something somewhat related. My other friend, an undergraduate student, was the first in nanolab to work on CT delta-sigma ADC as his thesis, and he has completed it. Many questions still remains though. It appears that CT delta-sigma ADC is now a quite hot topic in circuit designs, this is what I see in MWSCAS 2013 which I attended early this month in Columbus, Ohio. There are a huge amount of aspects to consider in the design of a CT DSM ADC, not only about transconductors (its linearity, distortion), but also proper filter coefficient designs, stability issues from loop delays, configurability, and possible alternative architectures. The analysis is also extremely difficult, the system contains both continuous and sampled parts: a linearized z-transform model is not enough to capture the behaviour of the system.

Sorry for getting too technical in the last paragraph, even I two months ago wouldn't understand the last two line I wrote on the previous paragraph, not to mention writing it. I really have to thank online lecture videos from Prof. Shanthi Pavan from IIT Madras which talked in a very detailed and clear manner about continuous time sigma delta ADC, a topic which may be just a side note in many ADC courses. He authored many recent papers in CT SDM ADC, and his papers helped me understand other highly-cited early works and textbooks in this field. It appears that I am not too good in maths and reading books with maths (very slow at it), so watching and learning through online lectures really works for me. I wish I could have done this much earlier.

My current plan is now to have "something" in our next planned chip tapeout, due in October. Which is about the same time as my next annual progress review, hopefully everything goes well as planned.

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4 Comments:

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Blogger Cia ling said...

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