Modeling the wires: a simple one

Speed or power. That was the question we asked on our last post. What if we want BOTH?

That's human nature. Human beings tend to be greedy. Sometimes a bit cruel too (e.g. i just squished a mozzy who wanted death: it bit me on my arm :D)

Back to interconnects, a fast and low power one that is. How do we get both of them?

In engineering, this daunting task is often called optimization. To do some silly optimization, one should model the problem with some mathematical expressions. To make life easy (that's what we engineers are here for anyway), modeling of physical properties and electrical characteristics of devices are normally made as simple as possible: simplification and approximation must be used whenever possible.

Alright, let us start with some maths from now.

Bakoglu, 22 years ago at 1985 modeled the wire system as consisting of a resistive driver, a lumped RC network as the wire, and a capacitive load at the receiver. You can read his paper titled "Optimal Interconnection Circuits for VLSI" for more details. From the way he drew the symbol of the load, which was the gate of a MOS transistor, it was obvious that voltage mode signaling was assumed.

A good approximation of the wire delay, he said, is:

T = 1.0 * Rint * Cint + 2.3 * (Rtr * Cint + Rtr * Cl + Rint * Cl)

and neglecting Cl, then

T = (2.3 Rtr + Rint) Cint

where Rtr = driver resistance, Rint = wire resistance, Cint = wire capacitance to ground, and Cl = load capacitance.

The driver's resistance, which is also the on-resistance of a MOS transistor is:

Rtr = (L / W) / (u * Cgox * Vdd)

And the resistance of the wire is a bit simpler, perhaps we all know this one from high school:

Rint = resistivity * Lmax / (Wint * H)

Wint times H is simply the cross-sectional area of the wire.

Now, he formulated the optimal cross-sectional area of the wire to be:

Wint * H = resistivity * Lmax / (2.3 * Rtr)

It seems that he chose the delay from wires to be roughly equal to the delay caused by the driver. Normally, the H is fixed for a certain technology. So the variable parameter we can play on is the width of the wire, Wint. The above formula enables us to find a minimum value of the interconnect width, with a reasonably low delay as possible. This idea is cited in Adler's paper "Repeater Design to Reduce Delay and Power in Resistive Interconnect" (1998).

Furthermore in his paper, Bakoglu explains about repeaters and inverter chains (cascaded drivers). Combining both will produce the shortest delay possible, where the extreme lower limit is the propagation delay of a lossless transmission line, where the speed is:

v = c / SQRT(dielectric constant of medium)