How late i realize

I'm using cadence(R) to do all my circuit simulations. And i am using the cadence 90nm generic process design kit library for it. And... just recently i have realized that working with such submicrometer technology nodes requires more caution: most of the secondary effects that you thought would not affect so much turns out to be ... affecting so much. Far out. (sorry can't swear in this blog)

Anyway, currently i'm looking at velocity saturation and mobility degradation effects on MOS transistors, and how do they affect EACH OTHER, and how would it affect the way i calculate Vds in velocity saturation...

Wish me luck.