Low Power Interconnects: Literature review early draft

Comments, suggestions, and questions are most welcome...

Overview

Technology scaling in integrated circuits allows an increase in operating frequency as well as transistor count per die area. To a certain extent it also reduces power dissipation due to lower supply voltage. The benefits obtained from scaling power supply voltage and threshold voltage had been discussed in [1] and [2], where delay reduction as well as power savings can be achieved. However, further scaling down threshold voltage will eventually cause subthreshold leakage current to increase exponentially with threshold voltage reduction. [3]

One other major obstacle in technology scaling is the increasingly larger delay and power consumption caused by the on-chip interconnects compared to gate delay and power dissipation. [4] explains that interconnect delay is a critical factor that limits circuit performance as they do not decrease as the gate delay scales down. Due to higher circuit complexity, total length of on-chip interconnects will increase, hence delay, power consumption, and reliability will become worse. This study will review current low power buses schemes, which includes low voltage swing buses and coding for minimizing power, as well as investigating the possibility to combine these methods with an error detecting mechanism to allow adaptive voltage swing buses.

This chapter will first discuss the modeling of interconnects, and then several optimal interconnect design techniques are reviewed, namely repeater insertion, low swing buses, coding techniques, and error detection mechanisms.

Interconnect modeling

A distributed RC model of a transmission line would be the accurate modeling of a single interconnect wire. However they are complex, hence the more simple RC network are normally employed. [5] Interconnects modeled as RC π3 structures are used in [6]. In [4], interconnects are treated as RC trees modeled as L or π-type circuits.

The effect of crosstalk between neighboring lines on interconnect delay is modeled by including a coupling capacitance parameter between adjacent lines in a bus. A discussion of the consequence of crosstalk to delay performance is discussed in [5], where a delay variation of 500% is possible due to Miller effect on neighboring lines where logic transition occurs. As can be seen from the ITRS 2003, the feature size and minimum pitch dimension decreases with technology scaling. [7] This implies that crosstalk would have a larger impact on interconnect delay in the future.

The derivation of coupling capacitance between conductors can be done using the publicly available 3D field extraction software such as Fastcap which had been used in [4].

Repeater insertion

Repeaters are placed in long interconnect wires in order to reduce the interconnect delay, where the quadratic relation between delay and wire length without repeaters becomes a near-linear relationship.[8], [5]

The problem with repeater insertion in the future is addressed in [9] and [8] where the number of repeaters required increases exponentially with technology scaling according to Rent's rule. [9] proposes an optimum repeater placement strategy considering power and delay trade-off.

Another method to reduce power of interconnects with repeaters is proposed by [10], where coding is employed to the bus in order to minimize crosstalk effect on delay. This combination however, had been shown to actually reduce power and delay on the 90nm and newer technology nodes, whereas a power penalty is introduced by the coding circuitry for the 130 nm technology node.

Low-swing buses

A review of several low-swing bus techniques is described in [6], where some improvements are also proposed.

In terms of the voltage swing range, low voltage swing buses may be divided into two categories. The first type has a voltage swing around the midpoint (Vdd/2), and the second type swings from Vss towards a low Vdd. [6] reviewed several low-swing on-chip interconnects particularly from the first type. These includes static drivers as well as dynamic driver circuits. In this paper, the authors also proposed improvements over the reviewed low swing buses in terms of signal-to-noise ratio. Among the methods reviewed, the differential technique seemed to have the most energy-delay savings compared to the others, despite its lower SNR and double driver and wire requirements.

In [11], an improvement was introduced over one category from [6], namely the dynamic diode-connected driver which has a voltage swing around midpoint. A preliminary simulation on 0.18um technology using Cadence shows that this technique reduces energy-delay by 32.13% compared to the full swing CMOS interconnect. However, this design has a lower signal-to-noise ratio compared to the full swing CMOS buses. [12] proposed a different interconnect design which has a voltage swing from Vss.

Coding techniques

Simple coding schemes are normally employed on buses to reduce the effect of crosstalk. This had been done in [7, 10, 13 , 14]. The main objectives of these techniques is to avoid opposite transitions in adjacent lines.

Coding had also been used for error protection for buses in [15]. In the paper, a simple parity check for error and a double and triple error correction using Hamming codes were used.

References

[1] R. Gonzalez, B. M. Gordon, and M. A. Horowitz, "Supply and threshold voltage scaling for low power CMOS," Solid-State Circuits, IEEE Journal of, vol. 32, pp. 1210-1216, 1997.

[2] A. P. Chandrakasan and R. W. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proceedings of the IEEE, vol. 83, pp. 498-523, 1995.

[3] J. T. Kao and A. P. Chandrakasan, "Dual-threshold voltage techniques for low-power digital circuits," Solid-State Circuits, IEEE Journal of, vol. 35, pp. 1009-1018, 2000.

[4] J. Cong, P. Zhigang, H. Lei, K. Cheng-Kok, and K. Kei-Yong, "Interconnect design for deep submicron ICs," 1997.

[5] J. M. Rabaey, A. P. Chandrakasan, and B. Nikolic, Digital integrated circuits : a design perspective, 2nd ed. Upper Saddle River, NJ: Prentice Hall, Pearson Education International, 2003.

[6] H. Zhang, V. George, and J. M. Rabaey, "Low-swing on-chip signaling techniques: effectiveness and robustness," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 8, pp. 264-272, 2000.

[7] S. R. Sridhara, N. R. Shanbhag, and G. Balamurugan, "Joint equalization and coding for on-chip bus communication," 2005.

[8] A. Maheshwari and W. Burleson, "Differential current-sensing for on-chip interconnects," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1321-1329, 2004.

[9] P. Kapur, G. Chandra, and K. C. Saraswat, "Power estimation in global interconnects and its reduction using a novel repeater optimization methodology," 2002.

[10] S. R. Sridhara and N. R. Shanbhag, "A low-power bus design using joint repeater insertion and coding," 2005.

[11] M. Ferretti and P. A. Beerel, "Low swing signaling using a dynamic diode-connected driver," 2001.

[12] P. Caputa, M. A. Anders, C. Svensson, R. K. Krishnamurthy, and S. Borkar, "A low-swing single-ended L1 cache bus technique for sub-90nm technologies," 2004.

[13] H. Po-Tsang and H. Wei, "Low power encoding schemes for run-time on-chip bus," presented at IEEE Asia-Pacific Conference on Circuits and Systems, 2004.

[14] S. R. Sridhara, A. Ahmed, and N. R. Shanbhag, "Area and energy-efficient crosstalk avoidance codes for on-chip buses," 2004.

[15] L. Li, et al, "Adaptive Error Protection for Energy Efficiency," presented at Proceedings of the International Conference on Computer Aided Design (ICCAD'03), 2003.