Why I didn't work on new circuit ideas
My thesis is about low swing interconnects. At the beginning, there was no clear idea on what method we should go through, or on what to do and how to do it. All that was given were circuits from other people. Then, my supervisor wants me to come up with new circuit ideas. That's fine, i thought. I straightly pursued this goal... which apparently proved fruitless due to my lack of understanding of even the basic circuits. So, my co-supervisor and I, even though a bit too late, decided that I should forget thinking about new and novel designs, but instead focus on FAIR COMPARISON. Fair comparison of different circuits appeals to me because, honestly, I don't quite believe the claims that's been made in papers proposing new 'novel' circuits. Look, there are many papers out there, claiming "...our new method shows up to 90% delay improvements and 50% power reduction than the circuit proposed in [1]..." Really? Is that true? Are you sure?? How did they compare it?
No, i wasn't sure. Then, early 2007 (can you see how late it is?) i attended an IEEE-sponsored guest lecture, by Prof. Oklobdzija, about energy-delay optimization methods. Wow, it gave me a huge insight on how to actually answer my questions. He suggested that comparing energy-delay tradeoff curve would be the best way to compare different circuit techniques.
Hence, this leads me to another problem: optimization. Well, actually in my early stages of work, i did do some limited form of optimization, which is fully trial-and-error-based. Apparently, that's not good enough, at least for me. So, my focus now is to find a formal method to design and optimize basic interconnect structures, so that i can then compare the energy-delay tradeoff between them, fair and square.
Sounds simple, but it's not. Prior to optimization, one needs to model the circuit accurately. Not just that, it should be accurate AND simple. Engineers hate complex formulas, and loves approximations. But that's sometimes impossible. No simple formulas can model short channel CMOS devices accurately these days. For instance, i had to discard all those simple basic CMOS drain current formulas from textbooks and use formulas from BSIM3V3 Spice manual instead. Many secondary effects that was neglected in the past can no longer be neglected in the 90nm technology node i am studying now. Not only does this different approach on short channel devices affect the way we estimate drain current, but also heaps of other things, most importantly for me: equivalent resistance, delay, power, and optimization methodology.
I think i'm more interested in modeling and optimization now than to actually come up with a new design. Just wish me luck so that i can submit my thesis on time. ( which is due december 2007)
No, i wasn't sure. Then, early 2007 (can you see how late it is?) i attended an IEEE-sponsored guest lecture, by Prof. Oklobdzija, about energy-delay optimization methods. Wow, it gave me a huge insight on how to actually answer my questions. He suggested that comparing energy-delay tradeoff curve would be the best way to compare different circuit techniques.
Hence, this leads me to another problem: optimization. Well, actually in my early stages of work, i did do some limited form of optimization, which is fully trial-and-error-based. Apparently, that's not good enough, at least for me. So, my focus now is to find a formal method to design and optimize basic interconnect structures, so that i can then compare the energy-delay tradeoff between them, fair and square.
Sounds simple, but it's not. Prior to optimization, one needs to model the circuit accurately. Not just that, it should be accurate AND simple. Engineers hate complex formulas, and loves approximations. But that's sometimes impossible. No simple formulas can model short channel CMOS devices accurately these days. For instance, i had to discard all those simple basic CMOS drain current formulas from textbooks and use formulas from BSIM3V3 Spice manual instead. Many secondary effects that was neglected in the past can no longer be neglected in the 90nm technology node i am studying now. Not only does this different approach on short channel devices affect the way we estimate drain current, but also heaps of other things, most importantly for me: equivalent resistance, delay, power, and optimization methodology.
I think i'm more interested in modeling and optimization now than to actually come up with a new design. Just wish me luck so that i can submit my thesis on time. ( which is due december 2007)
posted by Irfan at 9:48 am
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